// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1 (win64) Build 5076996 Wed May 22 18:37:14 MDT 2024
// Date        : Thu Nov  6 20:01:06 2025
// Host        : DESKTOP-IL2I0O0 running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode synth_stub
//               d:/programs/FPGA/multi_lia_pipline_ds/multi_lia_pipline_ds.gen/sources_1/ip/IIR_2_core_pipline_0/IIR_2_core_pipline_0_stub.v
// Design      : IIR_2_core_pipline_0
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7a35tfgg484-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "IIR_2_core_pipline,Vivado 2024.1" *)
module IIR_2_core_pipline_0(clk, rst_n, en_flag, busy, next_en_flag, 
  datin_bram_r_data, datin_bram_r_en, datin_bram_r_addr, daout_bram_w_data, 
  daout_bram_w_we, daout_bram_w_en, daout_bram_w_addr)
/* synthesis syn_black_box black_box_pad_pin="rst_n,en_flag,busy,next_en_flag,datin_bram_r_data[15:0],datin_bram_r_en,datin_bram_r_addr[11:0],daout_bram_w_data[15:0],daout_bram_w_we,daout_bram_w_en,daout_bram_w_addr[11:0]" */
/* synthesis syn_force_seq_prim="clk" */;
  input clk /* synthesis syn_isclock = 1 */;
  input rst_n;
  input en_flag;
  output busy;
  output next_en_flag;
  input [15:0]datin_bram_r_data;
  output datin_bram_r_en;
  output [11:0]datin_bram_r_addr;
  output [15:0]daout_bram_w_data;
  output daout_bram_w_we;
  output daout_bram_w_en;
  output [11:0]daout_bram_w_addr;
endmodule
